An example of multi-stage amplifiers are low-dropout (LDO) regulators which are linear voltage regulators which can operate with small input-output differential voltages. A typical LDO regulator 100 is illustrated in FIG. 1a. The LDO regulator 100 comprises an output amplification stage 103, e.g. a field-effect transistor (FET), at the output and a differential amplification stage or differential amplifier 101 (also referred to as an error amplifier) at the input. A first input (fb) 107 of the differential amplifier 101 receives a fraction of the output voltage Vout determined by the voltage divider 104 comprising resistors R0 and R1. The second input (ref) to the differential amplifier 101 is a stable voltage reference Vref 108 (also referred to as the bandgap reference). If the output voltage Vout changes relative to the reference voltage Vref, the drive voltage to the output amplification stage, e.g. the power FET (field effect transistor), changes by a feedback mechanism called main feedback loop to maintain a constant output voltage Vout.
The LDO regulator 100 of FIG. 1a further comprises an additional intermediate amplification stage 102 configured to amplify the output voltage of the differential amplification stage 101. As such, an intermediate amplification stage 102 may be used to provide an additional gain within the amplification path. Furthermore, the intermediate amplification stage 102 may provide a phase inversion.
In addition, the LDO regulator 100 may comprise an output capacitance Cout (also referred to as output capacitor or stabilization capacitor or bybass capacitor) 105 parallel to the load 106. The output capacitor 105 may be used to stabilize the output voltage Vout subject to a change of the load 106, in particular subject to a change of the load current Iload. It should be noted that typically the output current Iout at the output of the output amplification stage 103 corresponds to the load current Iload through the load 106 of the regulator 100 (apart from typically minor currents through the voltage divider 104 and the output capacitor 105). Consequently, the terms output current Iout and load current Iload are used synonymously, if not specified otherwise.
Typically, it is desirable to provide a stable output voltage Vout, even subject to transients of the load 106. By way of example, the regulator 100 may be used to provide a stable output voltage Vout to the processor of an electronic device (such as a smartphone). The load current Iload may vary significantly between a sleep state and an active state of the processor, thereby varying the load 106 of the regulator 100. In order to ensure a reliable operation of the processor, the output voltage Vout should remain stable, even in response to such load transients.
At the same time, the LDO regulator 100 should be able to react rapidly to load transients, i.e. the LDO regulator 100 should be able to rapidly provide the requested load current Iload, subject to a load transient. This means that the LDO regulator 100 should exhibit a high bandwidth.
The regulator 100 shown in FIG. 1a is an example of a multi-stage amplifier. Such multi-stage amplifiers 100, notably LDOs, are mainly unidirectional devices i.e. they can typically either source or sink current. Certain operating conditions may cause a substantial overshoot of the output voltage Vout at the output node of a multi-stage amplifier 100, which could damage a load 106 that is powered by the multi-stage amplifier 100. Example operating conditions are: a sudden removal of the load 106; the recovery from a transient in the supply voltage of the multi-stage amplifier 100, which has pushed the multi-stage amplifier 100 into deep dropout; a current being sourced into the output node of the multi-stage amplifier 100 by external pull-ups; the recovery from a current limit condition; and/or high temperature leakage from a pass device of the multi-stage amplifier 100.
A possible approach to addressing the problem of overshoots of the output voltage of a multi-stage amplifier 100 is the use of an active pull down circuit which is configured to remove an extra charge from the output capacitor 105. The active pull down may be implemented as a comparator or as an amplifier.
When a comparator is used and the current which is sourced into the output node is lower than the sinking capability of the pull down circuit, a sawtooth oscillation is typically observed at the output node of multi-stage amplifier 100 (see FIG. 3b). Such oscillations of the output voltage are typically undesirable, because such oscillations may negatively impact the load 106. On the other hand, when an amplifier is used, the compensation of such an amplifier may be difficult, if the capacitance of the output capacitor 105 of the multi-stage amplifier 100 is reduced. Furthermore, as the amplifier is typically not used under normal operation conditions (i.e. within an undervoltage situation at the output node), the current which is consumed by the amplifier of the pull down circuit is a burden on the minimum quiescent current for the multi-stage amplifier 100.